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Thread: DDR Fumbles, RDRAM Scores

  1. #31
    Ultimate Member Rugor's Avatar
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    I too agree with Quietstorm, but I think prttybean is guilty of a bit of an oversimplification.

    The issue with the nforce 420 chipset is not that the bus width is twice as great as the Athlon's FSB, but that the bandwidth is twice as high. So the CPU can't take the data in as fast as it's thrown at it. Now if you're using the onboard video and audio and they're taking some of that bandwidth then you might see an advantage to it.

    Simply having different sized datapaths for your FSB and Memory Bus doesn't automatically kill you. Remember the P4 uses a 64 bit FSB and two 16 bit Memory buses. However the Memory bus runs at 200MHz and the FSB at 100MHz so the effective transfer rate is the same: 64 bits X 100MHz quad-pumped = 2 X 16 bits X 200MHz quad-pumped. 3.2GB/sec = 3.2GB/sec. The only cost incurred is the latency penalty from stepping your data up and down to fit the paths.

    What I really want to see on the whole question of DDR vs RDRAM is a comparison between P4 based systems: one on Intel's upcoming Granite Bay dual channel DDR chipset the other on i850. Ideally the i850 will be running PC1066 RDRAM and the 533FSB while the Granite Bay would run PC2100 and the same FSB. Both types would have the same bandwidth and then we'd be able to see which, if either, is truly better.

    Now if someone ethical would only take over RAMBUS Inc.

  2. #32
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    I know this is out-of-topic...But check what a P4 can do with DDR...

    LMAO, its so unbelievable, especially when I can't even overclock my PIII 850 100MHz to 1.13GHz 133MHZ FSB...

    http://www6.tomshardware.com/cpu/02q...4_3000-01.html

  3. #33
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    The performance of a system is not only dependent on a single or couple of component, as in memory/CPU.

    Originally posted by prttybean


    I believe the problem why the athlon can not take davantage of the bandwith of the nForce chipset is the athlon has a 64bit bus the the memory bus of the nForce chipset is 128bits ie twice as wide as the athlon's bus
    Therefore to imply that the processor is unable to optimize on the bandwidth is not exactly accurate. We all know that one of the key limitations of the Intel P6 micro architecture was the FSB and the shared BUS architecture. However, a marked level of performance was achieved, not by merely increasing the MHz. But an integrated L2 cache, larger L1 cach and a higher FSB (from the conventional 66MHz. FSB) demonstrated a marked increase in overall performance.

    Now that we have more efficient processors and faster memory there is still another area of bottleneck that's yet to be addressed and implemented. The PCI BUS/communication between the Northbridge and Southbridge are still pretty ancient compared to other component improvement.

    PCI 32/33 = 133 MB/s
    PCI 32/66 = 266 MB/s
    PCI 64/66 = 533 MB/s
    PCI-X 64/133 = 1GB/s

    Until, Intel's Next Generation I/O 3GIO, Hub Architecture BUS, AMD's HyperTransport, LDT BUS, VIA's V-Link and others like InfiniBand, RapidIO system bottleneck shall still remain a major limitation.

    RAMBUS screwed up because of pure greed and their own stupidity, as copies of their emails was uncovered which incriminated them in unscrupulous practice within JEDEC.

    But, whatever it is Intel and Rambus Directors made their financial killing when the stocks were at their peak.

    RAMBUS and DDR SDRAM have their specific advantages and disadvantages in depending on the application.

    IMO, RAMBUS should focus more on technological advancement rather than merely increasing their profile on ?Wall Street.?

    As for memory prices we need to know more the facts rather just base it on our personal erroneous assumptions. Here is some interesting reading on the subject; PriceWatch listings this week that showed the 800-MHz 128-Megabit RDRAM selling at $3.40, compared with a 128-Mbit 266MHz DDR at $3.30. and Price parity evades DDR market


    Jerry


  4. #34
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    You are right about the limitations that PCs have, especially PCI bus for example. Just with a couple of IDE drives running in RAID 0 configuration is enough to utilized almost the whole PCI Bus bandwidth. But that is something totally different topic. I do like the idea of having multiple PCI buses, like the Athlon MPX chipset will have (correct me if I'm wrong), which will allow for more room, given the bandwidth limitations.

    Regarding factors such as L1 size (very small in P4 architecture, EXTREMELY BIG in ATHLON CPUs), L2 size, or increasing the FSB are factors in improving performance...No doubt on that, but keep those variables out of the equation, given that most P4 and AMD architectures are pretty much standard, except for the different makes on chipset manufacturers like SiS, VIA, Ali, Intel, AMD, etc. Regarding Memory alone, I personally expected more from such enhancements as the nForce chipset with Dual Bank Memory and the such...

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