Unreleased core photo of a .13 P3 Tualatin

[daveleau]

VERY cool stuff. Sysopt does it again. Thanks Scott/ RobRich!

[Undeadlord]

I guess I am just stupid : but that picture makes no sense to me. Does the average or even above average user, really have any idea what that picture means?


Undeadlord

[gr8vfr]

I have to agree...
The colors are very pretty, though.
But, could you explain what it all means?

Thanks.

[randy48]

You don't know what the different colors mean? Come on, look close. Think of it as looking down at a small city, do you see the streets? The blocks are blue...that's were the Intel "Blue Dudes" grew up

OK, so I'm stupid too! But I couldn't resist!

[RobRich]

I didn't major in EE, but I'll try to describe a few of the basics areas. The two large light blue blocks in the left regions are L2 cache memory blocks, each consisting of 256kb of storage. The smaller light blue blocks in the same area are the L1 cache regions. Most other uniform blocks with similar consistancy should be related to register regions, buffering, and branch prediction tables.

The various transistors paths and related parts compose the instruction pipeline, ranging from decode to execute to memory i/o. If I could offer any better exaplanation of these regions' physical properties, then I would be at work for Intel.

Robert Richmond

[RobRich]

Thanks for the positive comments Dave.

Upon examination of the core photo, notice the large cache storage areas. Also notice the close proximity of the controller stages to the cache region due to the smaller .13-micron die size. It appears the pre-release benchmark numbers floating around the net are correct, as the smaller length trace routes as compared to the .18u Coppermine could lead to a small reduction in latency. Overall, it appears to be a rather impressive design with great detail on efficiency and production yeild. I personally can't wait to see how the final revision Tualatin 512 performs against the Pentium 4.

Catch ya' later,
Robert Richmond

[zferenczy]

Thanks for the explanation Robert. We all think we know it all, but when it comes down to it we know a very little.

[beard]

ok, where can i see an identical image but of a PIII for comparison?

[MTAtech]

It reminds me of when President Kennedy was given the aerial photos of Cuba, proving that missles where being installed. He relied entirely on the expert's interpretation of the photos since he couldn't make head nor tail out of it himself.

My hat is off to those that can make sense of this photo.

[daveleau]

We all think we know it all, but when it comes down to it we know a very little.

Hey, speak for yourself, man. I DO know it all.

Sorry, couldn't resist.

What about registers. Are those synonymous with cache or are registers elsewhere?

Dave

[RobRich]

For comparison, P3 Coppermine core photos are available through the media relations portion of Intel's website.

http://www.intel.com

Registers are basically high-speed memory segments used for instruction storage within the execution pipeline. Check this out:

http://www.sysopt.com/articles/usparc-3/index4.html

Hope this helps,
Robert Richmond

[zenjive]

Does anyone know where I could find more core photos like this? Maybe some AMD cores or something in a nice shade of RISC? MIPS, Sparc... Cray?

On the other hand, it will probably all look the same, hehe.

[chass]

Are those features in the left half of the chip which appear to be solar panels, the 512KB of cache.I may be wrong but if the turns out to be the case, is half the chip is devoted to cache? anyone know how to decipher this?

[krazyknuc]

Oh, you're all ****-dumb !
Can't you see the little whatchamacallits that do the processing and the thingamabobs that are cache and the doohickies that, OH, what's the use, you'll never understand this technical jargon !

[RobRich]

All your questions are answered here .

Hopen this helps,
Robert Richmond