100mhz celerons

[cobain1crt]

Ok, judging from industry trends, Intels reputation, and limited information, I have come to the following conclusions on future celeron CPUs:

1. They will run at 100mhz.
2. They will have P3 Technology.
3. When put into a 66mhz board, multipliers will change accordingly.
4. They will only be available in PPGA.
5. They will have full speed cache.
6. There will be 128-156k of L2 cache.
7. They will be underclocked P3 CPUs.
8. They will overclock relativly well.
9. You may have to turn off L2 to overclock, as it will be the most powerfull clock lock.
10. The multiplier will be locked, but with an ABIT board, you can set the CPU signal to 66mhz and run at higher multipliers.
11. They will come with insufficient cooling.
12. They will have multipliers up to 7.5/8.0
13. People will be using them on the 133mhz bus.

[Roy]

I don't have time to answer point by point, maybe later. I should have added one thing to my IMPORTANT INTEL NEWS post:

Poking around I found a tidbit from The Register - U.K. 4/17/99

Due May 16 - P3-550 $744, P3-500 > $482

Due Sept. - P3-600 133 FSB, 256K L2 On Die $776, C500 $187

That C500 will be a 66MHz - 128L2 O.D. unit.

(I'll update the post.)

[This message has been edited by Roy (edited 05-13-99).]

[cobain1crt]

Where do you get data?

[nk4]

Cobain

In the front page of sysopt.com there is a link to the pentium3 price cuts, and from there to the 1999 price roadmap.
Level 2 cache is unlikely to go further than 128kb.
100Mhz is planned after coppermine's release.
P3 instructions? Given that its the low end market they are aiming, I doubt it, but hope I'm wrong.

Roy:
How do you know the celeron 500 will be 66Mhz
It is scheduled for a release along with the 600Mhz coppermine. Might as well shift to 100Mhz.

[BBA]

As far as Intel has published and indicated, All celerons will be designed for the 66Mhz fsb simply because they are designed to run on the EX chipset that is limited to 66mhz.

This is because the Celeron is deisgned only for affordable low end systems as to stomp out competition from AMD and Cyrex.

Celerons are all designed for the cheap 66Mhz chipset!

BBA

[MAGIC 8-BALL and THE ELF]

Cobain1crt writes when he should be reading. - 8-Ball

Yes. Even I caught the part about The Register - U.K! (nk4 missed it too.) - Elf

[cobain1crt]

You can only put so much of a multiplier on a cleron before going into 100mhz for higher speeds. Celerons always have been for the low end, but that have also always been the screwed up top-of-the-line chips, that is why so many people get to 450mhz with a celeron 300A. That is why I asume that they will have P3 instructions. And soon enough software will be optimized for P3 systems, and even the low end user will want to be able to use this.

[Roy]

Cobain1crt - you are doing it again. Celerons are not "screwed up" versions of Pentiums. Read. Study. Listen. Digest. Integrate. Synthesize. Get it! Please.

I hate to be crass, but "to assume makes an a** of U and Me". Like I said before and before that, don't assume. Learn.

[cobain1crt]

Celerons are screwed up versions of faster CPUs with different cache. They use the bad part of the board(that they might test say, 10 out of 150 chips and only like 2 go to the correct speed, so they turn them into celerons or slower same-class chips.

[BBA]

cobain1, the celeron is a totally different chip than the P2 altogether. The cache of the Celeron is part of the actual chip itself, it is made from a totally different die process. The only thing it shares with the P2 is the instructions and memory architecture. A P2 has the two L2 cache chips seperate from the cpu chip, mounted on the circuit board next to the chip. Totally different design! Completely different!

BBA

[cobain1crt]

That so? that book I read must have been bad, all well, then never mind, but I do know this: you can only multiply 66 for so long before you have to go faster, and even if they make a special chipset for higher multipliers, what are they gona do? 66x10?, 66x15?and if they did that, then they would loose compatability with present boards, something you do not do with cheapskate chips.As for the cache speed, i assumed that over a certain size it had to go slower to preven overheating.

[MAGIC 8-BALL and THE ELF]

cobain1crt - You are so incorrect! Please quit dumping misinformation upon the well meaning visitors to this realm. - 8-Ball

You've got him steaming, I've seen him low-level format more than one users' hard drive! - Elf

[800XL]

The original Celeron (266 and 300 not 300a and higher) were P2 cores (Deschutes)without the cache soldered to the PCB. The EXACT same core chip or die was used, but without any L2 cache at all. The 300A and faster Celeron have a different die (Mendicino) but the core logic is the same as a p2. The difference is that they put 128k of L2 cache on the die with the core. That means they are made by a different Fab, and are really different chips. The Celeron A is actually a more expensive die to make because it is more complex in terms of numbers of transistors. The external cache on the P2 could make it come out even in terms of total cost to make, at best, but I think the Celeron is probably a little more expensive. Sorta makes you think about Intel's strategy eh?

A little on the current topic: Intel does not care about cheapskate systems being compatible with anything. They make their bread and butter by making chips and selling them to computer makers. Computer makers don't make any money if people upgrade. The future Celeron will go to 100Mhz bus, but probably only after the PX goes to 133Mhz bus. Intel has been telling us all along how bad lower bus is, so they can't sell a cheap chip without it being on a lower speed bus than their flagship.

[This message has been edited by 800XL (edited 05-17-99).]

[Joel Kleppinger]

Oh, why not. I'll do a point-by-point analysis, though I'm skipping what's already been covered in the thread.

1. Intel has said they won't have 100 MHz FSB Celerons until early next year. I wouldn't be looking for them to go back on that.
2. When they do go 100 MHz, they are supposed to have the SSE instructions (I guess this is what you meant)
3. Sure would like to know where you came up with that. It's either bus-locked or unlocked... not partially locked depending on FSB MHz.
4. This goes without saying
5. Ditto
6. 128K. Dunno where you came up with the 156K idea.
7. I think you guys already covered the fallicies of this one.
8. Guesses, guesses. Don't guess 6 months in advance.
9. Ditto that.
10. LOL. You're wishing now.
11. LOL again. Who knows what Intel will do.
12. Of course. Perhaps they will go higher. No one really knows at exactly what clock speed Intel will change the Celeron from 66 to 100 MHz FSB.
13. We'll be using them on whatever we can run them on. =)

Oh, and btw, from apparent readings, it appears these same Q1-Q2 2000 Celerons will also be .18 micron process. Just an FYI.

From now on Cobain, please list (detailed if necessary) your sources when doing these lists. Give us some logical explanation for why you think the way you do... rather than just a singular list of things you think will happen.

Thanks from your loving Admin,

Joel

[This message has been edited by Joel Kleppinger (edited 05-17-99).]

[Roy]

Joel - Thanks for taking the time. You have said and reinforced what I would have said.

cobain1crt - Please pay attenion.

[This message has been edited by Roy (edited 05-17-99).]