Error Correcting Mem

[Nails9inmyhead]

I see most mem is Non-EC. Is it better to have EC? How does it work?

[BipolarBill]

ECC RAM has an extra bit called a parity bit. It aids in system stability at the cost of some speed.

Memory is good these days and 32-bit operating systems have good memory management. For desktop usage, ECC is overkill. It's only really necessary in servers and workstations that are mission-critical.

http://cr.yp.to/hardware/ecc.html

[Midknyte]

Unless you are running a server, you don't need ECC.

[Peter M]

Originally posted by BipolarBill
Memory is good these days

Best. Joke. Ever.

ECC RAM doesn't have an extra "bit", it has an extra eight bits (72 bits wide over standard 64). This allows the chipset's memory controller to store the payload data in a redundant encoding. On readback, this allows error detection and, to a certain amount of damage, correction.

What you get from it is perfect stability even though (very) occasionally bits in SDRAM do flip over (mostly because of being hit by subatomic particles from outer space). Also, actually damaged SDRAM cells get detected much more quickly.

As you can see above, you need to have a chipset that implements it. Most desktop commodity chipsets don't.

[BipolarBill]

Originally posted by Peter M

ECC RAM doesn't have an extra "bit", it has an extra eight bits (72 bits wide over standard 64).

Well, 8 x 8= 64 + 8 = 72. I was trying to keep it simple.

[Peter M]

Too simple ... the whole idea of ECC is exactly in that difference. The old "parity" 8+1 redundance only allowed for rudimentary error detection and no correction at all. ECC is 64+8, thus allows for a much wider so called hamming distance between valid codes in the entire code space. In terms of redundancy, 8x(8+1) does not equal 64+8 at all.

Parity has 256 valid codes in 512 total, meaning there's one invalid code for every valid one; ECC has 2^64 valid codes in 2^72 total, which means there are 255 invalid ones "around" each valid one. That allows for very solid error detection and even correction.

For those who are still with me, here's the theory of operation:
http://www.mdstud.chalmers.se/~md7sh...in/node21.html

[BipolarBill]

My head hurts.

Good info, that.

While we're on the subject, Peter, could you compare ECC and buffered/registered RAM? I know you've gone over it before, but I'd like to get it all in one thread. I'd like to make it sticky too.

[Peter M]

"registered" RAM electrically isolates the load imposed by the RAM chips from the system RAM bus. It does so by having both driver chips for the address lines (the registers) and a clock PLL chip on the DIMM.
So practically a registered DIMM imposes just one load to the system bus, while a normal double-sided DIMM would be 16 loads (18 w/ ECC) on the address lines and 4 to 5 on each of the four clock lines.

What's it for? Simply and only for making more RAM chips on the same bus possible. E.g. there are registered DIMMs with 36 chips on, and you can still have four or more of those. With standard unbuffered DIMMs that connect the SDRAMs directly to the system bus, that'd be electrically impossible.

Again, the system's chipset and BIOS must be capable of using these DIMMs.

While there technically would be four combinations of ECC and Registered/Unbuffered properties, in practice you'll only find registered ECC DIMMs for the server market and non-ECC unbuffered DIMMs for everyone else.

[BipolarBill]

Nails9inmyhead just earned himself a sticky!

Thanks, Pierre.

[Nails9inmyhead]

ROCK ON

[Swordfish]

Peter, ever thought about writing a book or a bible some day...u r a wealth of information.

thanx for the info.....and Bill thanx for makin it a sticky.

[Morn]

My hat's off to you Peter. Nice one.

May I add:
As Buffering adds a small propagation delay I can see its use only with ECC (it too adds delay), hence this combination is used for servers and, high (data) security use ie. business. The average home PC user is looking for speed. So non ECC Unbuffered RAM is the only other combination worth manufacturing.

Incidentally, as there are 8 bits in a byte (8b=1B) then if BipolarBill had said "parity byte" then we might not have had your accurate reply.

A parity bit allows Error Check (Detection) only. A parity byte allows Error Check and Correction.

I have seen some confusion created by claims that, for example, the ABIT KR7A RAID mobo needed registered RAM to work stably. Needless to say I used unbuffered DIMMS, with no problems. I followed the rules and didn't fill all the slots.

[BipolarBill]

Thanks, Morn. Welcome aboard!

[jbell255]

Check this out. Has a lotta info (for me at least)

Link:Slide Show

[Shockedder]

The extra eight bits in the ECC memory provide just the space for the extra data ; the correction and detection however is done by the chipset ; so if the chipset can't hack it , you just wasted $$ for nothing .

And the "very solid" error detection & correction is not so solid after all .
It can detect 1-bit and 2-bit errors , and can correct 1-bit errors .

Overall I think it ain't worth the commotion .