Ilya_S_K
06-18-2000, 08:13 AM
Caches on modern CPU models are using a set associative cache mapping technique. A set associative cache divides the cache into various sections, referred to as sets, with each set containing a number of cache lines. With an 8-way set associative L2 cache, each set contains 8 cache lines, and in a 16-way set associative L2 cache, each set contains 16 cache lines. Therefore there are 16 or 8 lines in cache per section of memory addresses.
Let's say the system has only 128Mb of system memory. How many sections there are and how many memory addresses each section contains?
One more question. Could anyone give me an idea how many memory addresses there are?
What would be the first and the last memory address?
Thanks, Ilya
[This message has been edited by Ilya_S_K (edited 06-18-2000).]
Let's say the system has only 128Mb of system memory. How many sections there are and how many memory addresses each section contains?
One more question. Could anyone give me an idea how many memory addresses there are?
What would be the first and the last memory address?
Thanks, Ilya
[This message has been edited by Ilya_S_K (edited 06-18-2000).]