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Grippen
01-25-2001, 08:17 AM
Does anyone know of a manufacturer currently shipping a dual (or more) Athlon or Duron board ?

daverme
01-25-2001, 10:01 AM
They don't exist. As I understand it, the processor architecture does not support it. I read recently that the next generation of AMD processors WILL support (is it SMP?) but they will not be compatibly with Intel processors.

RobRich
01-25-2001, 10:29 AM
The Athlon does support SMP operations, however all SMP calls are directly handled by the chipset's northbridge controller for the Athlon's modified Alpha EV-6 system bus architecture.

Motherboards will SMP support for SocketA Athlons will arrive sometime in Q2 of this year. AMD has already demo'd boards featuring its upcoming AMD-760MP dual-processor chipset.

Also, Micron is currently working on its next-generation Athlon Samurai-DDR derived chipset, with support for 8-way SMP and an L3 cache integrated directly into the chipset's northbridge controller. Sources, however, indicate that no Samurai-derived products will likely ever exist outisde of Micron test labs.

Robert Richmond

AnakiMana
01-25-2001, 12:11 PM
Let us not forget this article (posted on the main Sysopt.com page):

AMD Supercomputer
January 23, 2001 - 5:17pm, Mark Stubblefield

The University of Delaware's new machine, purchased with a $500,000 NSF grant
and dubbed 'Samson,' is expected to rank within the top 200 of the fastest
supercomputers in the world.

AMD on Monday added another Athlon-based supercomputer to its resume. The
company announced that the University of Delaware has installed a 128-processor
supercomputer based on 1GHz AMD Athlon processors and the Linux operating
system.

AnakiMana

Peter M
01-25-2001, 02:32 PM
Let me put this straight:

The Athlon or Duron CPUs do not support SMP. They don't have to.

We'll get dual Athlon/Duron boards though.

For increased throughput, AMD will not have a single shared CPU bus where both CPUs reside - instead, both CPUs will get their own bus. SMP coordination is in the chipset, and both CPUs enjoy full bandwidth on their respective CPU busses.

Meaning that the CPUs don't see each other, and don't need to talk to each other directly. Hence, no SMP capabilities needed in the CPU. And maybe funny configurations with two totally different CPUs are possible as well.

The first dual-CPU-bus chipset is on its way - AMD's own "760MP" chipset uses their 762 north bridge chip that does exactly that. First sample boards have just been sighted.

Regards, Peter

RobRich
01-25-2001, 02:44 PM
Peter is correct in theory. Assuming one wanted to utilize a Slot One Athlon processor with a Socket A Thunderbird, it would actually work with the 760MP chipset. Though, I doubt anyone would ever need this type of support.

Now only if AMD would have ever actually released its OpenPIC-compatible chipset, so I could configure an 8-way K6-3+ system. http://sysopt.earthweb.com/forum/wink.gif

Robert Richmond

Peter M
01-26-2001, 03:42 PM
No you couldn't - OpenPIC was only in AMD K5 and Cyrix 6x86; 6x86MX, MII, and K6 family processor don't have it.

Regards, Peter

wedor
01-26-2001, 05:53 PM
Tyan is supposed to release a dual CPU board in Q2.

RobRich
01-27-2001, 10:17 AM
Then what standard was AMD planning for the K6 series? The first K6 technical documents directly stated full SMP support. I was under the assumption that AMD choose to carry OpenPIC compatibility to the K6 because of this specification. Did another x86 non-APIC standard ever exist at AMD?

BTW, the OpenPIC documentation I have indicates all SMP-related operations were handled by the chipset's notherbridge controller, unlike Intel's CPU/chipset APIC specification. Considering this, why could OpenPIC not be configured for a variety of processors series?

Just curious,
Robert Richmond