200 Mhz Front Side Bus?

[ricomania]

Just what is meant by front side bus. I have an epox 7kxa mb w/a via kx133 chipset. w/AMD800Mhz cpu. I though it said 200mhz fsb but when I run diagnostics i get 100mhz fsb x8 reading. (also see that in on screen readout at bootup. Confused here. Can anyone explain this to me?
Also have installed latest via 4in1 drivers. have no problems at all except confised about fsb issue. Other diag redings are for the most part well above other systems in the benchmark comparisons. I use latest Sandra ver.

[Ruahrc]

http://sysopt.earthweb.com/forum/Forum5/HTML/003595.html

Read my post in there-it'll explain it.

Ruahrc

[Peter M]

The Athlon CPU bus uses DDR (double data rate) transfer method. Meaning that while the clock frequency is 100 MHz, two sets of data are transmitted during one clock period (on the falling and rising edge of the clock signal).

So the PR people like to call it a 200 MHz bus while it actually is 100 MHz DDR. The outcome almost is the same - data burst rate is exactly identical, yet all the handshaking can only be done at 100 MHz, not 200.

Regards, Peter

[ricomania]

Thanks you guys! Really appreciate it. Not only do I 100% completely understand your answers but I also understand what ddr is better.

[falcompsx]

sorry guys, but I believe you are wrong on this one. The Athlon's "200mhz bus" is real 200 mhz...between the cpu and the chipset. the memory is 100 mhz between the chipset and memory. so the 200 mhz bus is only to the chipset(AMD northbridge or ViaKX133) This is what AMD calls their Alpha EV bus or something like that. It does improve performance, but not near as much as DDR memory or a true 200 mem bus would do. It is more marketing then anything else. Besides, if it really did use DDR, it would beat the living s*** out of a P3 which it doesn't do. It is faster at 700mhz and below, and intel is faster at the higher speeds. Thunderbirds close this high speed gap, not positive which is faster though. Hey RobRich, am I right on this or am I the one missing the point?(sorry to use your name in vain MTP http://sysopt.earthweb.com/forum/smile.gif )

[RobRich]

The cpu bus is completely independant of the other buses. The DEC Alpha EV-6 architecture (AMD K7 uses modified form) doesn't actually have a true FSB. All the buses are independant, and are only connected at the chipset. It is also true that AMD uses dual signaling for their cpu bus. That means it will run at twice the memory bus speed. DDR memory support is not currently avaible, but expect it to seriously up the K7's performance when it does appear.


Here's more info:
http://www.hardocp.com/articles/amd/200bus.html

Also see my remarks regarding the Athlon bus architecture here:
http://sysopt.earthweb.com/forum/Forum3/HTML/006166.html

Happy Reading,
Robert Richmond

[Win_98]

With this in mind I am still confused
How can 100mhz bus become 200mhz
hmm technically it cannot be very well understood except by the amd technician themselve.
Actually it is very difficult to as I am having a hard time figuring how it work.
CPU is running virtually at 200mhz in that sense but not trully 200mhz like
133mhz FSB that we use on PIII

[Peter M]

OK, once again, more verbose.

VIA system chipset north bridges have all their busses decoupled a lot better than Intel's, meaning that there is more flexibility to system configuration:

The CPU Front Side Bus (FSB) may run at any speed suitable for the particular CPU. (Side note: CPU FSB is the speed that the CPU's bus connection to the chipset runs at. There's also a backside bus, this is where external L2 cache would connect, as seen on P-II or the original Athlon. Backside bus speed is entirely contained within the CPU cartridge, and was half the core speed in P-II and either 1/2, 2/5 or 1/3 core speed in Athlons.)

The DRAM bus can run at 66, 100, or 133 MHz (coming soon: 100 or 133 MHz DDR) regardless of CPU Front Side Bus frequency.

The PCI bus in turn is run at a certain fraction of the CPU FSB - 1/2, 1/3 or 1/4 (and 2/5 on super-7 chipsets) are allowable fractions.

VIA's Athlon chipsets have the CPU FSB at 100 MHz DDR, the SDRAM either at 100 or 133, and the PCI bus at 33.


Now DDR once again. The idea goes like this basically:

Normal single data rate transfers use a clock signal (which is a rectangular pulse signal). On every rising edge (0-to-1 transition) of that clock signal, data are transmitted, meaning that the states of the data signal lines change from the previously transmitted data to the new ones.

Now try to make that faster. You can't raise a frequency as you please - you'll soon hit signal quality and maximum load issues, as the trace lengths on the mainboard can't be shortened infinitely. (As seen with the first revision of the KT133, where the additional load of a 3rd DIMM made 133 MHz SDRAM unreliable - a signal quality/load issue.)

The brilliant idea behind DDR is: With SDR, the clock signal changes state twice as often as the data do. Clock changes from 0 to 1 and back to 0 every clock cycle, while the data lines change state only on every 0-to-1 transition of the clock, which is half as often. So on a 100 MHz clock, the clock signal changes state 200 million times per second.

Now consider that the clock signal line as it is has the same trace length as the data signal lines, and obviously its 0-to-1 and 1-to-0 transitions are read perfectly well on the other end of the bus.

The brilliant idea behind DDR is to use this fact, and allow the data lines to change state not only on the 0-to-1 state transitions of the clock signal, but also on the 1-to-0 transitions. The outcome is that the data lines are also allowed to change state twice as often as before.

Meaning that, without raising any frequency, effective data transfer rate is doubled. The extra signal quality required from SDR at the same frequency is quite minimal.

Regards, Peter

[falcompsx]

That just about sums up this topic, thanks rob and peter.

FalcomPSX

[mong_2]

a huh a what !