QDR in Vidcards?

[Hellmund]

I was just thinking about what they'll do next to alleviate the bandwidth problem on current vid-cards and remembered the article on QDR on sysopt quite a while ago. I don't recall whether they had the technology working or not but remember it being orientated around servers. I recall DDR being first released in Vid-cards so just wondering whether anyone heard anything?

[NDD]

I've read a while ago that QDR memory is available hardly as engineering samples, not operatible, for sure won't be on wide market in next year or two http://www.sysopt.com/forum/smile.gif

Best Regards ...

[Ruahrc]

If I'm not mistaken, QDR technology is out in the market and has been for a while.

Correct me if I'm wrong but the P4's "400MHz" system bus is really a QDR 100MHz bus.

And I'm fairly sure AGP4x which has been around for some time, is simply a QDR AGP bus. (AGP2x was a DDR bus)

Cost is probably what keeps QDR off of graphics cards, but I agree that they should implement it as it would bring great performance jumps on current chips.

Ruahrc

[Hellmund]

Sorry Ruahrc, I should have been more specific, I meant QDR SDRAM not QDR in general. I think DDR ram was first widely used in video cards and thought maybe we'd see QDR in newer vid cards in the next year or two. I figure theres a limit to how much they can tweak the memory subsystem until they just physically need more bandwidth. Just curious if anyone heard anythings recently and as ND said There dosn't seem to have been much progress in the QDR department. You'd think Intel would be looking into it as it would seem to be the perfect complement for the P4's FSB.

[Dputiger]

QDR is NOT the same as the Pentium 4 bus, which is 'quad pumped.'

Unfortunately, I don't remember WHY they aren't the same--but as I recall, Sysopt covered it in their Pentium 4 article--I'd check it out.

Also, QDR RAM won't alleviate the bandwidth problem in video cards, because its a never-ending race. The video complexity keeps growing, which pushes the need for MORE bandwidth out faster than it can be provided.

The solution--which every major card provider is adapting--is some type of more efficient memory structure or renderer. In the end, I think the Kyro II's tile-based rendering system will catch on. Though the Kyro II has some caveats, its ability to deliver better-than-GeForce2 GTS performance for less money is too dramatic not to pass up.

The fact is, if the Kyro ran at the speeds the GeForce2 GTS or Ultra did, it'd demolish the GeForce line of cards completely.

[Hellmund]

No it won't alleviate the bandwidth problem indefinitely cause like you said it's a never-ending battle as the cards keep getting faster. I'd assume it'll be like processors will likely be, they'll reach the limit in solid state and split off into dynamic or organic. QDR would alleviate the problem right now I would think though. It'd be a combination of efficient memory structure and highspeed memory which will yield the fastest card though.

The Kyro II doesn't support T&L last I read which could be a rather big drawback in current games out now so even if it was similarly clocked it can't beat the T&L on a GTS or Ultra. Excellent price and excellent card though in my opinion.

[Dputiger]

True enough, the Kyro II doesn't support T&L--but in most of the gaming benchmarks, even where it doesn't surpass the GeForce line, it DOES offer good performance--even in a T&L game.

My gut feeling is that the next generation of Kyro will support T&L, and that we'll see a much more aggressively clocked solution. That'll really make things interesting.

[NDD]

Dputiger, your "gut feeling" is so much correct http://www.sysopt.com/forum/smile.gif . Another article I read (I read a lot http://www.sysopt.com/forum/smile.gif ) was about semi-official info from STM, makers of Kyro chip, about forthcoming KyroIII, with T&L and higher clock rates (up to 200 MHz, syncronised).
Can you forecast the weather, also ? http://www.sysopt.com/forum/smile.gif

Best Regards ...

[Hellmund]

Where'd you read that article on the KyroIII?
I'd be interest to read.

[Dputiger]

You bet I forecast the weather. For a small fee, I'd be happy to tell you what its like outside my window right now--and make a prediction for five minutes from now.

[NDD]

http://www.sysopt.com/forum/wink.gif j/k

Sorry Hellmund, can't really give you the link, it's been a while, and I read tonz of stuff everyday ...

Best Regards ...

[jomiwic]

I think I saw info on the Reactor Crictical website http://www.reactorcritical.com/#l731. Just rumors though.

[Ruahrc]

Getting back to memory bandwidth...

Way back in the day CPU's and MB's were synched. 25MHz CPU... 25MHz MB. The technolgy for CPU speed progressed faster than MB tech so they started to use multipliers. Enabled faster CPU speed but we were getting slightly cheated as the MB was still slower.

My question is: What sort of performance would result if CPU's and MB's were synched again? 1000MHz CPU with an FSB of 1000MHz?

I'm assuming MB tech is harder to develop too because you not only have to develop a fast Northbridge, but you have to get a clean and stable signal to travel over long traces at high clock speeds as opposed to a tiny die?

Ruahrc

[Hellmund]

That would be one hell of a fast system. It'll never happen in our lifetime though. I'll let one of the other members explain why it'll never happen as I can't can't explain it well enough myself .

[NDD]

Hellmund, are you 112 years old and going to die ? http://www.sysopt.com/forum/smile.gif j/k ...
"Virtual" 400 MHz FSB (quad pumped 100 MHz) systems are out now, the P4s platform, so why do you think 1000 MHz barrier is so far away ?
To your question, Ruahrc, I guess you're pretty right, althought I don't like electronics myself, so I can't be an authority here http://www.sysopt.com/forum/smile.gif

Best Regards ...

[Hellmund]

Yeh but as you say it's Virtual. It's quad-pumped not a true 400mhz bus. The PCI is sill 33mhz. The AGP is 4X66 and we don't say it's 254mhz. He meant Everything is in sync. That means there is no DDR or QDR involved.

[AuraEdge]

He's right. To sync everything, the boards and the ram will have to synced at the Processor speed. I dont think it will come...probably ever
The highest true bus speed achievable is around 200Mhz these days. The highest RAM speed they have got so far is 233Mhz (In the Geforce2 Ultra).

It's like the turtle trying to catch up to the hare, its not gunna happen unless the hare justdecides to fall asleep (Processor speeds stale out).

[Hellmund]

There's only one real chance that the whole thing could be in sync again and that's still highly unlikely. Basically Intel and Amd are edging closer and closer to the limit that solid state technologies can reach. Eventually they should have to switch to something like optical or organic. If the transistion to one of those platforms took an EXTREMELY long time it's could......happen
. But that's still as I said very unlikely.

[samwichse]

Organic computers... ha ha. "Oh no, my computer died."

[NDD]

New errors of organic comps : "Got headache, please try later" http://www.sysopt.com/forum/smile.gif

All the problem with high-speed technologies is the time needed to develop such, and the cost, that eventually is so high that it stops the newly invented tech to get on the market widely enought. The memory limit of GF2Ultra is not the highest, what about L1/L2 cache memory in processors ? It running already at full core speed, already beyond 1 GHz ... and the ALU registers in P4 (kind of memory too, different, but still memory) are running twice the core speed, 3.4 GHz in P4 1.7 GHz ...
But as I said, imagine yourself plain 32MB videocard equiped with such kind of memory : let's say cache memory is maximum 10% of total processor cost, let's have 200$ processor (my 1 GHz T-Bird), it has 384k of cache memory (with total cost of 20$), to have 32MB - 384kx85.3=32755k. Now let's do - 20$x85.3=1706$ - only the cost of video memory http://www.sysopt.com/forum/frown.gif
Now, 256MB RAM is pretty common now, do the math yourself http://www.sysopt.com/forum/smile.gif

Everything is possible, but will you pay for it ?

Best Regards ...

[samwichse]

Seems like I read somewhere recently that someone was working on a "computer on a chip" but I can't remember where. I think that the idea is that the ram, processor, bridges and whatnot would all be on one big die. It'd be expensive as anything, but think of the performance increase. Wait, I found it: http://www.wired.com/news/topstories/0,1287,18058,00.html

[RobRich]

QDR is currently only available for SRAM-based technologies. QDR is not a new advanced technology, but only an extension to the DDR specification as ratified by JDEC. The QDR spec as defined by the latest memory manufacturer consortium conference is a low-latency form of dual-ported DDR SRAM. At this time, QDR-based SD-RAM is quite speculative. The only company I know currently researching a quad rate SD-RAM memory standard is Micron. To contrast, SRAM is a static form of memory used for high performance, low latency data storage, mostly for the intent of buffering the data during a transfer from varient speed storage mechanisms.

As for the Pentium 4, the processor bus uses a perpendicular, co-phased signaling technique to generate a psuedo-"2xDDR" bus. The base generation signal is derived from the primary system PLL at 100 MHz. The chipset uses this base signal to create two independant, but equally phased at 90 degress, signals along the shared processor bus. The P4 and chipset read both of these signals' rising and falling edges in the traditional DDR methodology. Two base DDR signals create a 4x timing pattern, thus the terminology of the "quad pumped bus".

In regards to a synchronized processor-to-chipset-to-memory bus system, the concept has several inherent flaws, especially at the production paradigm. At the PCB level, the signaling trace routes are measured in centimeters, not in fractional nanometers as found within a processor core. Spurious interference from radio frequency, magnetic pulse, background gamma/cosmic radiation, etc. would render such a bus unpoerable at this time. The only current solution known would be to integrate the processor, chipset, and memory within one die. Consider the poor yield rate for the massively complex Itanium or even the GeForce-3, and thus the slow clock speeds involved with these devices, even though each lacks onboard memory or chipset functions. The GF-3 base processing core requires upwards of 60 million transistors for operation. Imagine trying to integrate a complete system bus into one die. It could be upwards of 100-200 million transistors, assuming the system memory would be off die.

Also consider the design problems of a syncronous chipset, even if it was off die from the processor. Currently, most manufactureres are have difficult problems producing chipsets capable of ~300 MHz, even with the advanced characteristics of .18 micron fabrication techniques. Supplementing these designs with current off the shelve technologies (silicon on insulator, silicon germanium, pure silicon substrate, .13m fabrication, advaced dynamic gate switching algorithms, etc.), the effective operating frequency could possibly reach upwards of 1 GHz. This is still far from the speeds possible with current and next generation processor platforms, such as the 3 GHz Pentium 4 or 2 GHz Athlon Palamino.

I have little to offer on organic computer architectures, other than this technology is several decades away at the earliest. The only large change I forsee in the future in a transistion to a memory storage model based on a three dimesional architecture. When the market chooses to adopt this technology, we will no longer measure single system data amounts in mega- or giga-bytes, but in terrabytes or possibly greater.

Catch ya' later,
Robert Richmond

[This message has been edited by RobRich (edited 05-07-2001).]

[bwkaz]

Aren't memory arrays already three dimensional? You've got your row address strobe and column address strobe, then you read/write a byte. But that byte is 8 bits, which would be another dimension, right? Or am I way off on my assumptions somewhere?

Or were you talking about a row, column, and, say, depth address strobe, *then* 8 bits of data, so a sort-of-four dimensional array?

I think I just confused myself......

Bryan

p.s.: Yay!!! Petabytes or exabytes of memory!!! Yeah, I'm losing it, it's ok, leave me alone http://www.sysopt.com/forum/wink.gif

[This message has been edited by bwkaz (edited 05-07-2001).]

[RobRich]

Current memory standards use a flat approach, with only column and row addressing. The specific space can store a varying amount of data in accordance to the intended specification. The columns and rows form the x and y axises while the data being held can be representative of the specific points volume; or denisty, weight, intensity, etc. depending on how you want to examine the analogy. While the individual bit does represent a third characterisitc for the data operation, the actual read/write operation is addressed to a specfic two dimensional address space.

A true three dimensial memory model creates address space allocation for x, y, and z axises. Assuming a binary byte code memory storage technque is utilized as you above indicated, then the three dimensional data space would contain eight bits of data. For a 3D system, the memory controller would need to read/write to a three coordinate memory space, instead of the current standards two coordinate space (row and column), before directly addressing the specific bit needing to be accessed.

Upon examination of your appraoch towards this topic, one could rationalize how the arguement that today's memory appraoch is indeed three dimensional. However, a large portion of electronic eletrical engineers do everything "bass ackwards" in regards to derivative naming for their developed technologies. http://www.sysopt.com/forum/wink.gif

Robert Richmond

[bwkaz]

I see. Thanks!

Bryan

[This message has been edited by bwkaz (edited 05-08-2001).]

[NDD]

WOW, RobRich, you're so smart http://www.sysopt.com/forum/smile.gif
No kiddin' - you indeed very educated, way beyond your age, I also read few times your posts and reviews out of SYSopt, and they very very nice. Thumbs up !

Best Regards ...

[Hellmund]

Yeh, you obviously have huge knowledge of hardware, I was fine in the first post on the P4's bus etc but the memory post has me stumped....

[Hellmund]

What does the PLL you refer to stand for in relation to the P4. I just re-read the post and can't say I remember that from the article. I may have to find the article and read it again.

You said that they currently have only been able to reach 300mhz for a chipset, is that a true 300mhz or 150mhz DDR?

Thx for the information it's been very interesting to read

[jagman]

I read somewhere that at higher bus speeds a clock signal may be sent out before the previous one is recieved and that this could cause problems . Even if semiconductor tech evolves to the state where fsb speeds of ghz were possible we sure couldnt use the currently very lengthy copper tracks on pcbs.
The graphics cards are smaller compared to MB pcbs and therefore higher speeds .

[RobRich]

The PLL is a phased, locked-loop circuit which generates a base frequency signal. Take a look at your motherboard, the PLL will be a small chip located usually near the chipset's northbridge controller. Perhaps the most popular brand of PLL is ICS.

As for the chipset, I referenced 300 MHz in terms of a SDR timing signal. In terms of alternative signaling technologies, the P4's quad timed bus specs at 400 MHz, with a near future generation of P4's increasing to ~533 MHz (133 x 4) for increased performance.

BTW, thanks for the positive comments everyone! http://www.sysopt.com/forum/smile.gif

Robert Richmond

[hocheung]

It is impossible for me to convince my mom to buy me a new video card, as for my dad, it is kind of OK, but if my mom says no, then my dad is inclined to agree with her.

[hocheung]

wow! think of Quad pumped DDRSDRAM!
8 times the bandwidth of a normal SDRAM! Put that in an Athlon 1.33 and see what kind of results you get! Most certainly will beat the
P4

[NDD]

If I know something about this, this kind of RAM will probably feature higher latency, look at DDR SDRAM or RDRAM, for example. You'll just need more cycles for all this bandwidth, you can see it when DDR SDRAM scores only few percents higher then usual SDRAM

Best Regards ...

[RobRich]

DDR SD-RAM will offer greater performance returns when nVidia starts sampling of its "Crush" Athlon m/b chipset. The highest-tier offering of this product line is to offer a dual channel access technique to the DDR memory bus. This means a bandwidth increase upwards of 50-75% as compared to today's DDR capable chipset should be inorder, assuming this rumor proves accurate. Factor in the possibility of hardware pre-fetch for the Athlon Thoroughbred to better "hide" chipset to memory latency, then these next round of DDR solutions could prove quite powerful indeed.

Robert Richmond

[This message has been edited by RobRich (edited 07-24-2001).]

[Hellmund]

Why does the greater Bandwidth force a higher latency?

Also, the crush chipset is so AMD can build cheaper systems is it? It's to do with being able to have integrated video?

[RobRich]

Latency generally increases as the higher bandwidth is often dervied from a multiple bus design approach. The memory controller must access the memory array through multiple control routes as opposed to a single route with more traditional standards. Still, the latency aspect is usually unperceivable at best when proper buffering designs and prediction algorithms are utilized.

As for the nForce chipset, you are partially correct. The single-channel chipset will sell for approximately $45, but the much desirted dual-channel option is expected to reach well over $90. Even Intel's massively complex i850 design never exceeded $70 per unit in bulk shipments. Expect dual-channel nForce motherboards to sell in the $175-250 ranges, thus basically exluding this product from the value oriented market segment.

Robert Richmond

[NDD]

Happy now, Hellmund ? Your old thread is back http://www.sysopt.com/forum/smile.gif

nForce should really offer hell of performance, otherwise nobody gonna buy it. Besides, the o/b GeForce2 is already "slighly" outdated. This whole integrated business seems like a lot of risk nVIDIA takes ...

Best Regards ...

[Hellmund]

Well although the motherboard will place it out of the value segment it'll still sport a AMD athlon which for the moment is the cheapest and fastest processor. It still puts it way below an equivalent P4 board due to the I850 but the RDRAM and the P4 processor itself.

So the Higher bandwidth and more channels is kinda like the SMP with processors. Two processor clocking up a combined 1.4ghz won't be as fast as a single 1.4ghz, however if the single 1.4ghz isn't around yet then the dual@ 1.4ghz is still the fastest. So currently it's better for the Highbandwidth high latency until something with a single pathway and high bandwidth comes around....

Would be very interesting to see if the Nforce could be used with a Pentium 4. Dual channel DDR SDRAM would seem to give it almost the same bandwidth as RD800 RDRAM and DDR RAM has a lower latency so the P4 could really benefit. DDr is also much cheaper than RDRAM.... shame intel seems to be stuck in a deal RAMBUS as they'd be quite a bit more competitive it would seem.

Hey ND I think if they really wanted they could probaly stick a integrated GF3, the MX version seems to be a normal MX core stuck on the MOBO, it just uses the normal RAM though so a GF3 would be quite severely hampered by 266mhz RAM or 333mhz with high quality RAM, Still ain't the 500mhz and up they currently have http://www.sysopt.com/forum/smile.gif

YEh I am pretty happy this got responded too, also gratefull Rob took the time to answer my other post in the Community Forum on the ZDnet poll. Thx a great deal Rob, your always very informative and that's very appreciated http://www.sysopt.com/forum/smile.gif

[eagle1]

Yep.. Rob does knows his stuff.!!!
I'm glad we have people like him in this community.!!

[Hellmund]

Actually I think there really is only one Robrich, there are other people on this board with a lot of knowledge but Rob really knows his stuff on pretty well ALL current Hardware and Software it would seem. I think he's in his own league http://www.sysopt.com/forum/smile.gif

[eagle1]

Yeah.. Could I be like that someday..!!??????
Hmmmm I don't know.. I don't think my brain is big enough.!!

[Hellmund]

Well I know I can't, I left computer Engineering and am now doing Computer Science, I hated having to do all the management stuff, plus I had enough fun with physics in Highschool....Uni was just too much!
Wonder if Rob'l do that IQ test someone posted in the community forum.

BTW do you ever use ICQ eagle1? I've been waiting for authorisation for a while.

[RobRich]

TN state testing for certain advanced education programs placed my IQ at 150+ at age 14 (now 21), even though the test was intended for 4-year college graduates. Haven't taken any tests since, most seem to be a waste of time anyway.

I'll pass on EE, CE, and pretty much any other form of engineering as well. Working with advanced circuit dynamics did not sound too fun from my perspective.

I co-major in Mathematics and Scientific Application Development, though lost majority interest in college after completing my Associates of Science degree. I do plan to finish my BS in the future, most likely at the Florida Institute of Technology.

Onto the questions at hand...

The Pentium IV can actually utilize DDR memory, though the chipset to memory buffering mechanism must be highly optimized to offset the latency differences as compared to the P4's internal optimizations for RAMBUS.

Early obtained numbers from VIA's P4X266 chipset indicates that low cost PC-2100 DDR can offer performance within 5-10% of its more expensive PC-800 RD-DRAM counterpart. It is assumed this chipset uses a dual-channel approach, though no clear indication of this feature has been publicized.

SD-RAM is different story altogether. SD severely cripples the performance returns of the Pentium IV. Notice the lack of support and market attention directed at Intel's i845 chipset. The i845 design is the worst performing SD-RAM Intel chipset offering since the faulty i820 memory translation design.

Sad part is that pre-release numbers look favorable for the i845 with DDR memory. Results appear similar to VIA's P4X266. Worst yet, the current i845 natively supports both DDR and SDR, thus availability or compatibility not concerns. Specific Intel agreements with RAMBUS are still in effect through the end of this year, thus it will be Q1 2002 before the i845 can officially claim support for DDR memory.

And finally, looking towards nVidia for a competitive Athlon solution is definitely a smart choice. Regardless of cost, the nForce chipset is the highest performance AMD chipset available when operating in dual-channel mode. The only negative offset I forsee is the limitation of only 2 memory slots in while in dual-channel mode. Better buy enough DDR upfront, as upgrading later could prove quite expensive.

As for the integrated graphics controller, the nForce dual-channel has actually outperformed both the MX-200 and base MS designs in a variety of closed-door tests. Performance in certain programs even exceed the MX-400 design! The dual-channel approach allows for 128-bit transfers, while the Athlon utilizes 64-bit transfers. In rather basic terms, this means that 64-bit of the data pipe can be segmented for only onboard graphics operations. Thus the integrated solution has access to a 266 MHz 64-bit DDR storage array. That offers more sustained bandwith than any of the single card MX solutions be offered today. Assuming nVidia opts for a 175+ MHz clock rate, the nForce will be more than capable of scaling with its MX siblings.

Any rate, even the cheap single-channel nForce design will offer better integrated video performance than the lacking S3 Savage integrated chipsets offered by VIA. The only competitor with anything remotely capable of competiting with nVidia is SIS, though its is speculative whether the new single board SIS-315 graphics accelerator will be offered as an integrated option in future chipsets.

Catch ya' later,
Robert Richmond

[This message has been edited by RobRich (edited 07-26-2001).]

[Hellmund]

Yeh saw Tom's Review of the Trident Blade XP and the Sis 315. They were badly beaton by the MX400 but it wasn't really a fair comparison as they're really to compete with the MX200. They really did seem quite decent though, I'd say they'd be close in performance to the Hercules 4000XT with the orignal KYRO core. Doubt they'd handle overdraw quite as well as it does, wonder if St has considered putting there chips in integrated boards, the KYROII uses SDR and keeps up with GTS/RADEONS utilies DDR RAM. The original KYRO only ran at 115/115 so they could simply underclock it a little and it'd work fine with the PC100 or even possible with a slight overclock PC133. It they allowed for the core/mem to be out of sync it'd offer a very cheap yet quite powerfull little integrated solution.

[eagle1]

Hi Hellmund.!! I'm studying Computer Science too.!! Was in Electrical Engineering but.... took my circuits classes and didn't appeal to me the electical stuff (maybe because I didn't pass the 2nd one--hahaha).

About ICQ.!!
I'm always connected... Are you sure you have the right number????

[prexaspes]

Man, I suck. I got kicked outta my house THE DAY I graduated high school. No college for me. I'm a painter. I hope to eventually go mainstream with my computer business I have on the side. Given the choice and money, I'd go for Nuclear Physics because subatomic particles rock and cosmology is cool. But basically I'm a big dumb moron.

[Dputiger]

Hey Prex,

It's all relative. I know a lot of people that know more about me than computers. I know a lot of people that no less.

And frankly, given a choice, I'd hire you to paint my house before any nuclear physicist. http://www.sysopt.com/forum/smile.gif

[Hellmund]

When I had that virus lost my ICQ and I had two profiles on there.....picked the wrong one http://www.sysopt.com/forum/smile.gif Was wondering why I wasn't receiving any messages from anyone......that profile had been dead for two years. I quit Computer Engineering cause I was quite unhappy, it was really boring, our uni especially, they specialise in teaching Design Management so we had to do a lot of large group activities and other stuff, quite a lot happier in Computer Science. Unfortuately in the catch-up I have to do some 'elementry' stuff in Infotech. I juse learnt about mind-maps for an hour-an-a-half. You know what I'm talking about?

[prexaspes]

Hey man, I don't know anything about computer other than what I need to know. I learn as I go along. But I can also tell you I've never had a problem I couldn't fix...

BTW - I don't really paint houses anymore. I just got promoted, I guess. I'm a 24 year old foreman running two different jobs. High schools, of all things. Industrial painting, I'd guess you'd call it.

[Hellmund]

Yeah I know what you mean, it may not be the best and easiest solution but I can always find a way http://www.sysopt.com/forum/smile.gif Of course Sysopt helps http://www.sysopt.com/forum/wink.gif