cache associativity

[mr adam]

what is cache associativity and how does it affect performance thanks
85rPny

[RobRich]

To further aid in bandwidth, the full-speed L1 cache uses a 4-way set associative architecture. In simple terms, this means the cache will buffer data at four different points within the memory array. Since data can be found at four different memory locations, the cache controller does not need to expend precious CPU overhead for address searching the entire cache region before the needed information can be found. While a 1-way associative architecture provides the best performance, a 4-way architecture provides more effective bandwidth with lower clock latency.

This is from SysOpt's recent Sun UltraSparc-III article, available here:

http://www.sysopt.com/articles/usparc-3/index.html

Robert Richmond