himmo
04-16-2008, 12:06 PM
Hi All,
I am modeling the memory architecture of the Intel Xeon Dual Core using a simulation tool but have not been able to find any good resources online about the functionality of the Caching Bus/Bridge Controller.
Can anyone provide me with this info that I require; I want to know how the CBC handles requests from the two cores to the shared cache and the RAM.
Please...this is really urgent as I have a deadline coming up very soon and I have to complete the model.
Thanks
I am modeling the memory architecture of the Intel Xeon Dual Core using a simulation tool but have not been able to find any good resources online about the functionality of the Caching Bus/Bridge Controller.
Can anyone provide me with this info that I require; I want to know how the CBC handles requests from the two cores to the shared cache and the RAM.
Please...this is really urgent as I have a deadline coming up very soon and I have to complete the model.
Thanks