Pentium 4, is the FSB "Really" 400mhz ?

[Richard_Cranium72]

Is this another deal like the AMD Athlon with it's 200mhz FSB,, EXCEPT, oops folks, we were just kidding, it's only 100mhz !

Does the system really run at 400mhz FSB.

What memory does this require if so ?

Intel's comments->>

" 400 MHz system bus
Hyper-pipelined technology
Rapid execution engine
Execution trace cache
Advanced transfer cache
Advanced dynamic execution
Enhanced floating point/multimedia
Streaming SIMD extensions 2 "

http://www.intel.com/pentium4/index.htm?iid=feature+head&

BTW, this is the 2nd time I posted this question TODAY, the first musta fell into the dark abyss of Intel lovers http://www.sysopt.com/forum/smile.gif

DrVette

[BBA]

Don't know...but they do the same trick with the Rambus bus.

[DanU]

From http://developer.intel.com/design/pentium4/datashts/249198.htm

The 400 MHz system bus is a quad-pumped bus running off a 100 MHz system clock making 3.2 GB/sec data transfer rates possible.

Using megahertz to describe bit rates can be confusing. Hertz is a measure of periodicity, not data rate. The only way the data lines are going to be running at 400MHz is if it transmits an alternating string of ones and zeros... 0101010101. If it transmits 001100110011... its going to look like a 200MHz signal. It's more accurate to say that the bus runs at 3.2Gbps using 64 data lines running at 400Mbps. But of course everyone uses MHz and Mbps interchangeably and it just causes a LOT of confusion.

[1Old Fart]

Ahhhh.........Got It!
.
.
.Nope.......Dont got It D)

[Hellmund]

Robrich explains it well here http://www.sysopt.com/forum/Forum4/HTML/005066.html
It's not actually a 'true' 400mhz bus, else how would they make the 1.7ghz proc, 4.25X400!! or the 1.5ghz. From what I understood it's a dual 100mhz DDR FSB.

[Hellmund]

Doub post .....

[This message has been edited by Hellmund (edited 05-14-2001).]

[DanU]

Ok... I took a closer look at the intel spec sheet. The data bus does indeed run up to 400MHz. For every clock cycle coming from the motherboard, four bits of data are transmitted. The signals would look like this:

________ ____
/ \ /
clock / \ /
/ \ /
/ \________/

1 2 3 4 1 2...
__ __ __ __ __ _
/ \ / \ / \ / \ / \ /
data \/ \/ \/ \/ \/
/\ /\ /\ /\ /\
\__/ \__/ \__/ \__/ \__/ \_



ARRRRG... the fixed width font isn't working right. Someone help me out with this UBB code!!! Well here's the link:
http://members.nbci.com/solder/sysopt/4xclock.txt

Data is transmitted at the clock rising edge (1), top (2), falling edge (3) and bottom (4).

This isn't new at all! In fact, this is exactly what AGP4x does.

The internal PLL uses the 100MHz system clock as a reference. The PLL multiplier is 17x for the 1.7GHz chip, 15x for the 1.5GHz chip.

Hellmund, I think you confused the data bus with the system clock. The PLL does not use the 400MHz data bus as a reference.

[This message has been edited by DanU (edited 05-14-2001).]

[RobRich]

I'll try this one more time:

Instead of using a direct Phase Locked Loop (PLL) clock to natively generate the 400Mhz bus signal, Intel has chosen to adopt a new timing standard. The base global clock generator will operate at a mere 100Mhz, but a new timing circuitry will be employed for final clock signal generation. This timing circuit generates two identical, but 90 degree co-phased, signals that travel along the same bus. When being read, both the falling and rising edges of both clock signals are used, and thus a 100MHz signal is interpreted as 400MHz. Intel has definitely been doing their research to create such an advanced clock generation technology.

http://www.sysopt.com/articles/p4/index4.html

Dan is correct in approach, as the bus can transfer data at four key signal points. The total driving signal is based upon a
DDR derived" technology, but applies the DDR read/write methodology upon two co-phased signals traveling along the same bus. The PLL generates a 100 MHz drive signal, but the chipset operates at the full 400 MHz. Next time anyone examines a working i850 board, try touching the chipset's Northbridge controller during intense operation. http://www.sysopt.com/forum/wink.gif

Robert Richmond

[Hellmund]

Forgive me if I say this wrong but I'll try and clarify what I meant. The PLL generates the 100mhz signal, now this is a DDR signal that uses the rising and falling edges so it's essentially 200mhz. Then I meant that it transmits two of these signals at the same time, essentially the 400mhz. I suppose I didn't write this dual 100mhz DDR FSB as well as I should.

[Hellmund]

Also DanU, the original question was in reference to the systen clock not the data bus.

[Richard_Cranium72]

That's OK Hellmund, cuz the good DrVette don't know the diff between "Data Bus" or "System Clock" http://www.sysopt.com/forum/smile.gif)

[DanU]

Definitely much confusion going around.....

So i guess there are three... maybe four different clock signals that we're talking about.

One is the mobo-generated 100MHz system clock.
One is the cpu-generated 1.7GHz clock that is derived from the system clock
One (or two, depending on how you look at it) is the 2 x 200MHz signal that drives the data bus. This is also derived from the 100MHz system clock.

Hmm... I just noticed that my little clock diagram displays properly on IE but netscape seems to screw it up.

[RLT65]

Okay, now I have a question. The Vcache uses RAM as a disk cache, what speed does vcache run on a P4 system?

RT

[Richard_Cranium72]

Thanks for the input guys.

That helps, now I know for an upgrade of RAM I don't have to look for 400 mhz RAM sticks http://www.sysopt.com/forum/smile.gif

A rumor floating about has Intel in a tizzy trying to get the mobo's sorted out, something about chipset woes, I think.

[RobRich]

The i850 chipset is far from perfect in regards to compatibility. Many people have suffered stability concerns when utilizing PCI devices that demand a long latency timer, such as professional sound cards or 3D accelerated PCI video cards.

To contract, assuming one uses quality components that meet Microsoft's WHQL and HCL standards, then the i850 should operate perfectly fine.

BTW, the i845 is rapidly approaching with support for SD-RAM solutions (SDR and DDR) and integrated video (plus AGP slot, like i81x series). Good news for those seeking a lower cost Intel system in the near future.

Catch ya' later,
Robert Richmond