*lol* Is this what they are teaching A+ people now?

[Nighthawk]

Reading through my A+ study guide (I want to be prepared before I take the test) and I found the following _glaring_ error:

Heading: Dual Inline Memory Module (DIMM)

The final type of memory package is known as a DIMM (Dual Inline Memory Module). DIMMs are dual-sided memory chips that hold twice as many chips as a SIMM. (And, except for the fact that they have chips on both sides, they look just like a SIMM). Generally, the DIMMs you'll run into will hav eeither 72 or 168 pins. Some DIMMs are 32-bit, but more and more are 64-bit and only have to be installed one at a time in Pentium-class computers.

Gee, does this mean that the single-sided 128mb RAM modules in my P3V4X are now called SIMMs and the double-sided 72-pin thingies in my 486 board are DIMMs? http://www.sysopt.com/forum/smile.gif

Also,

Most memory chips are 32-bit; so are several of the processors. You have a problem, however, when you have 32-bit memory chips and a 64-bit processor. To solve this, you must either install the SIMMs in pairs (always installing multiples of two-this is especially true for Pentium computers) or change to a DIMM installation (discussed next)


Aren't the only 32-bit chips 486s? Pentium chips are 64-bit internal (or 2 32bit pipelines, whatever) and that's why they need either 2 SIMMs or 1 DIMM. 486 CPUs will work with one SIMM.

They also claimed that PC800 RIMMs have a 1.6GB/second bandwidth, giving it more than DDR SDRAM. According to Crucial, PC1600 has 1600 MB/second bandwidth and PC2100 has 2100 MB/second bandwidth. Hmm...

I filled out the form to tell them about it and thought it funny enough to post about. It's especially glaring when this is the new test study guide that won't be rehashed for the next 2-3 years.

BTW, it's a 2-book and CD set from Sybex, authored by David Groth

Edit-> They don't know RAM, I don't know how to spell http://www.sysopt.com/forum/smile.gif

[This message has been edited by Nighthawk (edited 04-19-2001).]

[welsh wizard]

What was the press date of the Sybex book, and who was the author?
WW

[Nighthawk]

Copyright 2001 SYBEX Inc. (insert legal blather here)
Library of Congress Card Number 00-112011
ISBN: 0-7821-2806-8

A+ Core Harware Study Guide Third Edition.

Author: David Groth

[BBA]

Aren't the only 32-bit chips 486s? Pentium chips are 64-bit internal (or 2 32bit pipelines, whatever) and that's why they need either 2 SIMMs or 1 DIMM. 486 CPUs will work with one SIMM.



That doesn't quite sound right to me.


I thought a DIMM had two sides of 32 bit memory banks. IE: your single sided 128M DIMM is really half of a 256M DIMM...if the other side was populated, but it is referred to as a 'DIMM' simply because of it's packaging.

Experience would indicate this is true, as I have seen motherboards that would only recognize the ram on one side of a dimm, not the other, in bad slots. This was verified by placing a 64M DIMM ( single sided ) into a slot that would recognize 64M properly when only half the ram of a doublesided 64M DIMM would register in the same slot.

Edit: For accuracy...


[This message has been edited by BBA (edited 04-22-2001).]

[darkclaw]

30 pin simm = 8 bit
72 pin simm = 32 bit
168 pin simm = 64 bit
density of ram on simm/dimm makes no difference. Whoever wrote that needs well...to relearn everything correctly

[BBA]

Do you have a link for reference for that design criteria?

I'd like to see just so I can be sure.

[darkclaw]

BBA if your post refered to me just go to the local Barnes and Noble, Books-A-Million, Walden Books, what ever and read Scott Muller's Upgrading and Repairing PC's 12th Edition. Specifically the chapter on Memory.

[BBA]

I'll try that...I've been reading the Exam Cram A+...no mention of that information there. I also could not find it in the NewRiders and the SAMs Publishing books.

[BBA]

Found a few things:

DIMM Description (http://www.crucial.com/Crucial/pvtcontent/memorytype.asp?memtype=168-PINDIMM)


168-pin DIMMs are commonly found in Pentium and Athlon systems. Each 168-pin DIMM provides a 64-bit data path, so they are installed singly in 64-bit systems. 168-pin DIMMs are available in FPM, EDO, 66MHz SDRAM, PC100 SDRAM, and PC133 SDRAM.


72 pin SIMM Description (http://www.crucial.com/Crucial/pvtcontent/memorytype.asp?memtype=72-PINSIMM)


72-pin SIMMs are commonly found in older desktop computers, such as the 486 and early Pentium models. Each 72-pin SIMM provides a 32-bit data path, so they can be installed singly in 32-bit systems (486 models) but must be installed in pairs in 64-bit systems (Pentium and Athlon models). 72-pin SIMMs are available in FPM or EDO.


30 Pin SIMM Description (http://www.crucial.com/Crucial/pvtcontent/memorytype.asp?memtype=30-PINSIMM)


30-pin SIMMs are commonly found in older desktop computers, such as the 386 and 486 models. Each 30-pin SIMM provides an 8-bit data path, so they must be installed in banks of 4 in order to communicate with 32-bit systems (such as 486 models).


Hope that helps some.

[Bovon]

While searching for answers as to should the northbride on VIA chipset boards be fan/heatsink cooled, I ran across the following at Corsairs Q & A BBS...

http://www.corsairmicro.com/main/bbmain.html

Would somebody care to comment on this?, Some ppl are reporting very high northbridge temps, many have added fans/sinks to the boards that come without them, some have fried the northbridge due to overheating. Any thoughts concerning ram related overheating the northbridge, or any other reasons for the northbridge to overheat would be welcome.

At Corsair's Q & A BBS
Question
: Does registered vs unbuffered work the same way/does registered ram cause a performance hit that unbuffered does not have? When should you decide that registered is the way to go vs unbuffered?
Answer
Simply said: registered modules can be arranged into bigger memory pools. An unbuffered module has 8 or 16 chips (9 or 18 with ECC) and using 4 modules brings the total to a maximum of 64 chips. And guess what, this is exactly the figure used in the rule-of-thumb: if you want to use more than 64 RAM chips on a motherboard, then go for registered or the poor little Northbridge chip will get fried trying to drive so many RAM chips.
Registered is more expensive, and only needed for large pools of memory. For desktop or "simple" workstation use it's unnecessary. In servers, I ALWAYS use registered.
Performancewise registered isn't really slower: it's usually CAS3, like normal memory modules. Now Corsair has CAS2 modules, but they're also working on CAS2 registered modules...
Another thing: registered modules are almost always fitted with ECC - which the desktop _also_ doesn't really need, and the server _also_ really DOES need. MAkes the modules more expensive yet.

Desktop: go with non-ecc unbuffered.
Server: Take Registered ECC
inbetween: weigh your choices.



[This message has been edited by Bovon (edited 04-23-2001).]

[BBA]

How about this:

Desktop: Registered will not physically fit.

SERVER: Put Registered in if it will fit, because if it's made for registered...nothing else will work. ( Thats how Compaq servers do it )

[Nighthawk]

The chip population on each side does not affect how many bits the memory interface is.

What affects how many chips are on it is the memory density. For example, 8x32mb DIMMs are double-sided 32mb DIMMs and are the highest that a VX board can take.

However, when chip densities enabled more than 2mb to be stored in a TSOP (Thin Small Outline Package, the term for the types of surface mount chips on the DIMMs and some SIMMs), 8-chip and eventually 4-chip 32mb DIMMs were produced.

The same is happening now with 4-chip 64mb DIMMs, 8-chip 128mb DIMMs, and 16-chip 256mb DIMMs. Anyone remember when a 256mb DIMM required 32 chips? I do, I worked at a store that sold them. (It looked like a double-high double-sided 128mb DIMM).

Again, the (S or D)IMM refers to how many banks of 32 bits it can virtually create. A SIMM with 16 chips, each of 2mb, will appear as one 32mb bank and require another SIMM to create two banks of 32mb each (so that a Pentium can address it). A DIMM with 16 2mb chips will register as two 32-bit banks, each of 16mb.

[SoopaStar]

SIMMS...must be installed in pairs in 64-bit systems (Pentium and Athlon models).

Sheesh...someone show me an Athlong board with simms please? Think that guy is refering to the K6 family. ****...if this is all the A+ is..maybe I should get my cert.

Paul

[Nighthawk]

I'm going through the book and making notes of every error that they say. Most are minor, like picture captions or calling a LIF a ZIF, but I found one last night calling AMD 486 procs socket 5 instead of 3.

I still can't believe that none of this was caught by the editor, since much of it is so obviously wrong.

and BTW, I think the book had that saying that SIMMs are double when used in Athlon systems http://www.sysopt.com/forum/smile.gif

I saw a DEC Alpha Station and since the bus for the processor itself is 128-bit, DIMMs have to be installed in pairs. Gotta love that bandwidth!

[darkclaw]

Simms with an Athlon?!?! And I thought PC 150 was a big enough bottle neck. Well...remind me not to send any of my written work for these guys to be published.

[Noomatik]

A note about processors:

there tends to be general fuzziness about the use of terms like "32-bit" or "64-bit" in relation to processors -- i found this especially true in textbooks!

if you go to the source, you'll see that Intel themselves defines this in specific terms. the capacity of a processor's internal registers determines its general design type. Pentiums, and all their relatives, are in fact considered *32-bit* processors by this definition.

Intel 32-bit processors include the 386, 486, and Pentium(s) -- including Pentium Pro, Pentium MMX, Pentium II, Celeron, Pentium III, Pentium 4 (you get the picture). yes, since the original Pentium, multiple pipelines and such have been implemented which potentially help speed up processing. but if we are going to base our definition of a processor's "bit size" then we need a specific standard.

in that regard, see this page:
http://www.intel.com/procs/support/faqs/ppfaqx2.htm
(specifically, look at Question #5)

Intel's answer goes on to explain that part of the reason for misconception is that the Pentium does possess a 64-bit data bus. this is not quite the same as saying the processor is 64-bit.

Intel has of course been developing what they consider a 64-bit processor; it is known as the Itanium (peculiar name, but we've come to expect such things from Intel, eh?). this next generation Intel design has been referred to as IA-64 (Intel Architecture-64 bit), and the prior generation is now designated as IA-32. interesting.

i do find it slighty amusing and mostly frustrating that we have textbooks and study guides which are supposed to present technical facts for people to study to pass various tests and such, and yet the level of accuracy for some of these materials is a bit less than what i would have ordinarily expected. ironically, for such technically oriented content, you would think that editors would have plenty of methods and tools available for verifying such information -- i mean, there's this thing called the Internet for goodness' sake. if you have a question about Intel-compatible CPUs, how about checking out Intel's website -- after all, they make the darned things, they ought to know a little bit about them, right?

anyway, sorry for the minor rant. i hope this information proves useful.

[and no, i don't care for proper punctuation and capitalization]

[Coliseum]

1) Registered and Unregistered (SDRAM):

Registered and Unregistered (aka Unbuffered) DIMMs are identical if you compare the edge connectors, and both will fit in the same socket, let it be a server or a regular desktop. (I´m assuming both are 3.3V 2nd generation DIMMs)

The chipsets used on desktops won´t usually recognize a Registered DIMM. Chipsets used on servers usually recognize both Registered and Unregistered, but won´t accept a mix of them.

Please note also that Registered DIMMs will impose one clock penalty on the CAS latency. So, if the DIMM is CL3, you'll nedd to add one extra cycle for the data to latch in the register.

2) Buffered and Unbuffered (EDO):

EDO DIMMs, on the other hand, can be "Buffered" or "Unbuffered". Due to the fact that the term "Unbuffered" came chronologically first, most people will refer to "Unregistered" SDRAM DIMMs as being "Unbuffered", which is essentially the same thing, since it denotes a lack of any extra components between the DRAMs and the address and control lines on the motherboard.

Since "Buffered" DIMMs are 1st generation DIMMs, one of the notchs in the edge connectors will be on a slightly different position, and this is the reason why Unbuffered/Unregistered/Registered DIMMs won´t fin in a socket designed for Buffered DIMMs. (I´m assumng in this case that the operating voltage is the same, for the other notch indicates the operating voltage for a particular DIMM).


3) Mb and MB

It helps to use the correct terminology: MB for MegaBYTES and Mb for MegaBITS. The former usually denotes a module density, the latter usually denotes a memory chip density. I say "usually", because obviously you can use them as you will. But using "mb" to denote both Megabytes and Megabits can cause a lot of confusion. http://www.sysopt.com/forum/smile.gif


4) Banks:

Regarding to the bank issue: If the addressing range on the DRAM chips is the same as the addressing range of the DIMM module, the DIMM will be single bank. If the addressing range of the DRAM chips is half of the addressing range of the DIMM module, the module will be a dual bank one.

Example 1: a 64MB DIMM using 64Mb DRAMs, each organized as 8Mx8.

A 64MB DIMM will have a 8Mx64 organization (no ECC in this case). If the memory chips are 8Mx8 each, you'll have a single bank with all addresses wired together, forming a single bank with a 8M addressing range.
Eight chips will do the trick, since each DRAM will supply 8 bits, and 8 of them will form the 64 bit data bus. If you need ECC, add one more chip and you´ll have 72 bits.


Example 2: another 64MB DIMM (8Mx64) using 64Mb DRAMs, with each DRAM organized as 4Mx16.

In this case, the addressing depth of the DRAM chips is only 4M, and each DRAM supplies 16 data bits. In this case, 4 DRAMs will be enough to form the 64-bit data bus, but the addressing range will be limited to only 4M. You´ll need 4 more DRAMs, forming another identical bank, and then you'll have a dual bank DIMM module (8Mx64).

The difference is that in the 1st example the chipset can address all 8M selecting just one bank (or "row", using the chipset manufacturers terminology). In the 2nd example, the chipset must select the fist bank when addressing in the 0-4M range and select the second bank when addressing the 4-8M range.

Hope this helps to clarify a bit (pun intended) http://www.sysopt.com/forum/smile.gif

>B^)x


[This message has been edited by Coliseum (edited 04-26-2001).]

[SylvainG]

Hi !

The SIMM and DIMM acronym refer to something very basic.

SIMM (30 or 72 pins) have one row of pin numbered 1 to 72 (or 30). Hold one with the notch on left and look at the number. You have 1 on left and 72 on right. Turn it around and you have 72 on left and 1 on right. So there 72 pins IN-LINE, they are the same on both side of the module.

DIMM (168 pins) have two rows of pins and they are different on each side. If you hold one with the smallest group of pins on left, you have pin 1-10 in the first group, 11-40 on the next and 41-84 on the last one. Turn it around and you have the rest of the pins 85 to 168 going from right to left. This look more like PCI/AGP pins arrangement and this is why it'a a dual (row) in-line memory module.

[Conmidhe]

I've been studying for the A+ exam since January using 3 different books, a formal classroom with quilified instructor, and half a dozen web sites. The errors being talked about here are NOT at ALL uncommon. On average about 1 in 20 questions in the practice exams have a serious flaw. Just yesterday I came across a statement that it is not possible to set a swap file in Win 9x. Just because its now called Virtual memory doesnt mean its not a swap file. If you look it up 12 places 11 of them will say ...Virtual Memory(swap file)....
The problem with the A+ guides out there is that they're not about correct information, they're about selling a product.

PS(don't even get me started on the way the questions are worded)

[Coliseum]

Ah! Don't forget that Registered DIMMs introduce an extra latency cycle on read commands (i.e., if the DRAMs are CL3, the module is called a CL3 too, but will be in fact a CL4).
That's because of the extra clock cycle needed to clock the address and control bits on the register.

184 pin DIMMs for DDR also can be found in "Registered" and "Unregistered" configuration.

Most (if not all) Registered modules will have ECC too, because they're meant primarily for servers, and ECC is usually a "must have" for them. http://www.sysopt.com/forum/smile.gif

Cheerio,

>B^)x

[araaraara]

IF you use a textbook with "incorrect" information and your answer on the test was marked wrong, could you get the mark changed if you showed them the errors in the book?

[Conmidhe]

The exam is in a computer format and the people that give the exam are in no way affiliated with those who write the study guides. They charge $132 per half, thats $264 for the OS core and the Hardware core which make up the A+ certification exam. If you fail either half you have to take them both again and PAY for BOTH again. So I'd guess that there aint a chance in hell they're gonna let you argue your way into a passing grade thereby avoiding another $264 bill.

[Wombat]

I passed my A+ last year and I must admit, some of the text books had some serious errors. Also some of the questions I had in the exam weren't covered in the books or in the catch up course I took.
If you were starting from ground zero with no knowledge of computers and just followed these books you would fall flat on your face when you entered the real world.
The only thing I can say is experience and common sense counts when you run into these kind of situations.

[This message has been edited by Wombat (edited 05-02-2001).]