absalom
08-21-2002, 10:10 PM
AMD's 2700+ to use 333MHz FSB
Larger cache, SOI? Sounds like Mr Barton to us
By Mike Magee: Wednesday 21 August 2002, 09:17
SOURCES SAID that AMD's next speed step, after today's announcement of the 2400+ and 2600+ Athlon XPs, will be a 2700+ which will use a 333MHz front side bus (FSB).
But AMD may also attempt to introduce other features into the 2700+ if engineers can make that work.
Those could include Barton like elements such as SOI (silicon on insulator) and a 512K cache but that's dependent on whether the designers can make these elements work in a 2700+ chip.
The target date now for the 2700+ is October but while the engineers can introduce a 333 FSB with few if any problems, we understand that they are having difficulties making the SOI process work.
As there are only a few weeks to go before the marketeers want to run the 2700+ into the marketplace, it would seem to us touch and go whether those problems can be safely ironed out before the launch date.
AMD's processor cup and roadmaps rather overfloweth. Not only is the firm re-engineering its Dresden fab ready for the launch of 64-bit Hammer processors, it also has mobile chips and MP (multiprocessing) chips to make.
Against the background of what would seem to be a bitter price war between it and Intel, and due to continued uncertainty in the PC marketplace, that adds up to quite a bit of internal and external pressure, we'd venture to suggest.
AMD decided to switch in the launch of the 2400+ and the 2600+ faster than people expected. Intel's price cuts are related to those introductions. The chip war between them both is on again with a vengeance.
While that's good news for consumers, we wonder, however, just what this is going to do to both companies' margins in the next months ahead. µ
http://213.219.40.69/?article=5053
from the inquirer :t
Larger cache, SOI? Sounds like Mr Barton to us
By Mike Magee: Wednesday 21 August 2002, 09:17
SOURCES SAID that AMD's next speed step, after today's announcement of the 2400+ and 2600+ Athlon XPs, will be a 2700+ which will use a 333MHz front side bus (FSB).
But AMD may also attempt to introduce other features into the 2700+ if engineers can make that work.
Those could include Barton like elements such as SOI (silicon on insulator) and a 512K cache but that's dependent on whether the designers can make these elements work in a 2700+ chip.
The target date now for the 2700+ is October but while the engineers can introduce a 333 FSB with few if any problems, we understand that they are having difficulties making the SOI process work.
As there are only a few weeks to go before the marketeers want to run the 2700+ into the marketplace, it would seem to us touch and go whether those problems can be safely ironed out before the launch date.
AMD's processor cup and roadmaps rather overfloweth. Not only is the firm re-engineering its Dresden fab ready for the launch of 64-bit Hammer processors, it also has mobile chips and MP (multiprocessing) chips to make.
Against the background of what would seem to be a bitter price war between it and Intel, and due to continued uncertainty in the PC marketplace, that adds up to quite a bit of internal and external pressure, we'd venture to suggest.
AMD decided to switch in the launch of the 2400+ and the 2600+ faster than people expected. Intel's price cuts are related to those introductions. The chip war between them both is on again with a vengeance.
While that's good news for consumers, we wonder, however, just what this is going to do to both companies' margins in the next months ahead. µ
http://213.219.40.69/?article=5053
from the inquirer :t