An article about DDR RAM, speed tests compared to PC133

[Richard_Cranium72]

Lots of people testing DDR, this is just another I thought was good reading.

Makes ya wonder if it's worth the effort..
http://www.realworldtech.com/page.cfm?ArticleID=RWT012801000000&PageNum=2

[Mungla]

Doc,

I think the problem is that processors or yesteryear were built for SDRAM. Once we get more processors, such as the PIV, which have faster memory busses, we should see the potential for DDR-SDRAM. Does anyone know if Intel is going to be releasing a PIV based on DDR? I haven't heard anything about one, which kinda makes me wonder what Intel's pulling.

[RobRich]

Check this out for information regarding the P4 and DDR:

http://sysopt.earthweb.com/articles/intel-roadmap/index2.html

Intel's Brookdale chipset will offer DDR memory support for the P4, but this platform will not appear until Q1 2001 at the earliest. Surprisingly, the P4 does perform decently well with SD-RAM for desktop applications like IE, Word, and Excel. However high-bandwidth software like games, 3D, multimedia, and scientific applications clearly show the advantage of dual-channel RAMBUS support (nearly 1500 MB/s bandwidth).

Intel will be releasing the official figures regarding the P4 and SD-RAM at the upcoming IDF convention.

The issue present is not only bandwidth, but latency. Johan over at Aces recently wrote an excellent article detailing the technical issues regarding the P4's performance characteristics. Check this out:

http://www.aceshardware.com/Spades/read.php?article_id=20000190

My recent articles here at SysOpt regarding the P4 also further supports several statements regarding performance characteristics. Clearly the P4 is best suited for SSE2. When processing a SSE2 SIMD operation, the P4 benfits two ways. The SIMD nature of SSE2 allows for the compaction of several commands to be excuted with minimal (sometimes single) clock cycle duration. The SSE2 instruction set can lower latency and theoretically lead to a 2x (peak) bandwidth increase as compared to traditional x86 instructions when utilizing a 128-bit instruction execution path.

http://sysopt.earthweb.com/articles/p4/index.html
http://sysopt.earthweb.com/reviews/pentium4/index.html

Catch ya' later,
Robert Richmond

[Mungla]

Like any of us, on a resonable note, I hope that the PIV and Palomino are both extremely successful. If either one fails, the winning side will become a whole new monopoly.

Has Intel released any statements inregards to releasing a non-neutered version of the PIV? I mean, a PIV that has the full amount of cache that it was originally designed for? That's the one to chunk your cash apon, in my opinion.