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RAM Technology Primer: CAS Latency- Page 1/1
September 22, 1999
By
Heidi Monson
Recently, RAM manufacturers have bandied about the terms CAS Latency, CAS2, and CAS3 with great relish. They make it sound like CAS2 is a huge improvement over CAS3. Is it, or is it mainly hype? For that matter, what on earth is it?
Simply put, CAS Latency is a number that refers to the ratio - rounded to the next higher whole number - between column access time and the clock cycle time. It is derived from dividing the column access time by the clock frequency, and raising the result to the next whole number. This formula is:
CL >= tCAC/tCLK
Where:
CL is CAS Latency.
tCAC is Column Access Time.
tCLK is Length of Clock Cycle.
For example, if the tCAC is 20 nanoseconds and the tCLK is 10 ns. (as with a 100 Mhz. bus), then the CL must be 2. However, if tCAC is 25 ns., then CL must be 3, since 25/10 = 2.5.
SDRAM Basics
So, what does all this mean? To understand, we need to get into other memory timing factors. First, an introduction to a few more terms:
RAS* - Row Access Strobe
CAS* - Column Access Strobe
tRCD - Time between RAS and CAS access.
tRP - Time to switch between memory banks.
tAC - Time to prepare for output.
*RAS and CAS are normally written with a line across the top.
The SDRAM basics of how data is transferred from memory to the CPU are as follows:
The CPU sends a signal specifying the memory row and bank that it wants to access via the RAS line.
After a specific period of time (tRCD) the CPU sends a signal on the CAS line, specifying the column it wants to access.
After tCAC (column access time) the data moves to the output line, from where it is transferred with the next clock tick.
The CPU expects the data to appear upon a specific clock tick after sending the request.
In PC100 SDRAM, this process takes about 50 ns. for the first transfer. However, in burst mode it takes only one clock cycle for the next three, or if a different column is required, the time required by tCAC (CAS Latency).
CAS Latency Specifics
To keep things as simple as possible, the clock cycle referred to in this article (unless otherwise specified) is based on a 100 megahertz bus. Since the clock cycle is the inverse of the bus speed, it is defined here as 10 nanoseconds. On a 100 Mhz. bus, data transfer takes about 2 ns. According to specification, tAC is 6 ns. It takes about 2 ns. for the signal to stabilize.
6 ns. (tAC) + 2 ns. (stabilization time) = 8 ns. 8 ns. + 2 ns. (transfer time) = 10 ns. = 1 clock tick
Thus, in burst mode (the three data transfers after the first one requiring 50 ns.) data can be transferred in one clock cycle.
Often, SDRAM modules are defined by three numbers, such as 2-2-2 or 3-2-2. The first number refers to CAS Latency, the second to tRP, and the third to tRCD. Note that these numbers mean different things for different bus speeds. Following is an example of calculating these numbers for 100 Mhz. (1 clock cycle = 10 ns.):
tCAC = 25 ns.
25 / 10 = 2.5 - round up to 3
3-2-2
tRP = 20 ns.
20 / 10 = 2
tRCD = 20 ns.
20 / 10 = 2
However, if these figures were calculated at 133 Mhz. (1 clock cycle = 7.5 ns.), the results would be:
tCAC = 25 ns.
25 / 7.5 = 3.33 - round up to 4
4-3-3
tRP = 20 ns.
20 / 7.5 = 2.67 - round up to 3
tRCD = 20 ns.
20 / 7.5 = 2.67 - round up to 3
As you can see, the second example would not be valid in a 133 Mhz. system, as a CAS Latency of 4 is not allowed in the SDRAM specification.
With all the hype about CAS Latency, usually written as CAS2 or CAS3, just how important is it? In general, the importance is nominal. CAS3 means, at 100 Mhz., that the amount of time required for the first memory access in a burst is increased by less than 10 ns. Divide that by 4, to average the increased time across four bursts, and you have an improvement of less than 2.5 ns. over CAS2. However, if you are considering overclocking the bus, then it could be critical.
CAS Latency and Overclocking
To overclock the bus, you must be sure that the memory can handle it. In this case, you’ll need to make assumptions about tCAC, unless the manufacturer provides it, which is highly unlikely. You can, however, infer it from tCLK, as defined by the bus speed, and the CAS Latency of the SDRAM. Take, for example, SDRAM with CAS Latency of 2 on a 66 Mhz. board.
1 / 66,000,000 hz. = 15.1 ns.
CL >= tCAC / tCLK
2 >= tCAC / 15.1 ns.
tCAC <= 30.2 ns.
Because the SDRAM specification calls for a maximum CAS Latency of 3, the worst-case scenario for overclocking to 83 Mhz. is:
1 / 83,000,000 hz. = 12.0 ns.
3 >= tCAC / 12.0 ns.
tCAC <= 36.0 ns.
Thus, in this example, the difference between the slowest possible column access time, 30.2 ns., and the maximum time allowed by the SDRAM specification, 36.0 ns., is 5.8 ns. Obviously, this isn’t a large gap. If the memory module is made by a reputable manufacturer - which can generally be determined by whether the name is stamped on the module - then the odds that it is overclockable from 66 Mhz. to 83 Mhz. are good. Of course, if you can get the tCAC from the manufacturer, you can be certain.
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